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introduction |
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| The company has been involved with hierarchical
Design for Testability methods and practices since 1983. We are
passionate about achieving the optimum fault detection and management
capability for a given system within commercial project constraints.
We can provide FMECA, Fault Tree and Testability analyses and we
have worked ‘clean sheet of paper’ and ‘near COTS’
projects. We are confident in our ability to solve your testability
and integration problems through hardware, software or hybrid solutions.
We have been
associated with testability and BIT concepts from sub-component
level through to system level both in military and civil environments
(MILS STD 2165, DEF STAN 00-13). We have been involved with all
aspects of the design life cycle, writing specifications, equipment
source selection, hardware and software engineering, system modelling,
database development and maintenance, system integration testing
and product support (ILS). We have worked with partners from the
USA, Germany, Spain and Italy and have a FEANI registered chartered
engineer amongst our staff.
The company has been associated with several Design
for Testability courses, seminars and workshops and our engineers
have presented papers at IEE and IEEE sponsored events.
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projects |
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| We have experience of testability design and
analysis on the following projects :
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Industrial
Controls PLC and Drives control equipment
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GEC
Industrial Controls |
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Eurofighter
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BAE Systems
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Tornado
MLU |
BAE Systems
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New En
Route Centre (Air Traffic Control)
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IBM |
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MRA4 (Nimrod) |
Boeing |
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COTS source selection and integration |
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| We have worked Commercial Off The Shelf (COTS)
and ‘Near COTS’ project solutions. Lessons learned ?
well where do we start, it is essential that RM&T (and more
widely ILS) requirements are recognised and understood at the proposal
stage and that they are respected to the extent that they are worked
concurrently with hardware and software design. We see the selection
and rugedisation of COTS products as a real but necessary challenge.
The elegant use of COTS equipment embedded into systems design is
the way forward for Military hardware but technology insertion strategies
and schedules should be part of bid requests and proposals as an
offset to capability growth requirements and obsolescence issues.
To this end we feel the following are key to the success of any
COTS/design hybrid :
- Comprehensive requirements analysis and understanding
by all parties
- Definitive interface control documentation
- A committed system integration team
- Contract wide commitment to manage requirements
creep
- A close working relationship with suppliers and
customer
- Managed strategies to promote technology insertion
For Testability, the challenge is extracting and
utilising the optimum level of self-test capability from a COTS
item and enhancing or underpinning this with robust communication
protocols and polling mechanisms. In short a hybrid hardware/software
solution.
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research |
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The
company has sponsored research associated with the requirements
and capabilities (both hardware and software) needed to support
modular avionics architectures at each hierarchical level
including 1149.1 and .5 ‘boundary scan’ architectures.
The research addressed distributed processing architectures,
modular software, software testability, and the application
of artificial intelligence and expert systems techniques to
system resource management.
Further
research is now being supported, this work is focused on the
automatic and dynamic management of distributed system resources
in healthy and fault condition scenarios. We are particularly
interested in the management of decaying systems i.e. all
spare system resources have been utilised, further faults
will inevitably cause system degradation. How can a system
manage its own demise whilst supporting critical system functions
to the point of sacrificing the intelligent core ? |
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training
courses |
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| We are able to offer ‘overview’,
‘tailored’ or ‘focussed’ Design for Testability
training dependent on your needs. |
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links |
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contact
us |
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